Semiconductor capex consolidation is creating systemic concentration risk
Three companies now account for substantially all leading-edge logic capacity. The geopolitical and operational implications are larger than the headline numbers suggest.
The semiconductor industry has spent the last decade telling a story about resilience: the CHIPS and Science Act in the United States, the European Chips Act, the equivalent industrial policies in Japan, South Korea and India. Each was framed as an effort to reduce dependence on a single geography for the most strategically important manufactured product in the global economy. The headline numbers are large. The on-the-ground reality of leading-edge manufacturing concentration has barely moved.
TSMC continues to operate the only commercially viable 3-nanometre and below production at scale. Samsung is the credible second source on a multi-year lag. Intel Foundry is the third name in the conversation, but its leading-edge process roadmap continues to be the subject of technical and commercial scepticism that successive earnings cycles have not resolved. Outside those three names there is no leading-edge logic foundry with credible volume. The capex curve required to enter is now such that even sovereign-backed competitors face decade-scale, tens-of-billions-of-dollars commitments before the first wafer ships.
The dependency is not just geographic
The geographic concentration in Taiwan is the part of the story that policy attention has focused on, and it is not exaggerated. But the bigger structural issue is the concentration of the equipment supply chain that any leading-edge fab — wherever it is built — must rely on. ASML's extreme ultraviolet lithography systems are the binding input. There is no second source. The toolset for the next generation of high-NA EUV is even more concentrated, with multi-year lead times and deliberate export controls layered on top.
This matters because the substitution argument used to defend the CHIPS-era investments — that new fabs in Arizona, Dresden, Kumamoto and Hsinchu collectively reduce single-point-of-failure risk — only holds if those fabs can operate independently. They cannot. A serious disruption to the equipment, materials or service chain that originates in the Netherlands, Japan, or Taiwan would propagate to every fab regardless of where it sits.
The pricing structure that has emerged is consistent with a tightly concentrated supplier base. Wafer prices at the leading edge have risen, foundry utilisation remains high, and the largest customers — Apple, Nvidia, AMD, Qualcomm, the hyperscalers — have moved to multi-year capacity reservations rather than rolling purchase orders. Smaller fabless customers report longer lead times and tighter allocation than at any point in the post-pandemic era.
For strategy and risk teams the implication is that the diversification thesis on which much of recent industrial policy was built needs to be re-examined. Building geographically distributed fabs reduces certain failure modes. It does not change the fact that a small number of companies, in a small number of countries, control the inputs without which none of those fabs can function.
The rational response is not to abandon the diversification programmes. They will pay off in time. The honest response is to recognise that the concentration risk that AI, defence and consumer electronics now collectively rely on is structural, that the policy instruments to address it operate on a decade timeframe, and that the operational planning for any organisation whose products depend on leading-edge silicon needs to assume that the supply chain will remain tighter than it ought to be for the rest of the decade.
